Electrical Subsystems

This section describes the major electrical components of the Raptor board. Figure 6 show a block diagram of all the main components of the Raptor SDR.

Xilinx Zynq UltraScale+ MPSOC

The Raptor SDR includes a Xilinx Zynq UltraScale+ XCZU9EG-1FFVC900E FPGA. The processing system in a Zynq Ultrascale+ MPSOC features the ARM flagship Cortex-A53 64 bit quad-core processor and Cortex-R5 dual-core real-time processor, and a single Mali-400 graphics processing unit (GPU) with pixel and geometry processor and 644 KB L2 cache. All SOM memory and digital interfaces connect to the Zynq through the Processing System (PS) or Programmable Logic (PL). The Analog Devices AD9361 RF transceiver is connected through the Zynq Ultrascale+ PL.

Source: Xilinx, Inc.

For more information, refer to the Zynq UltraScale site [1].

Analog Devices AD9361 Transceiver

The Raptor SDR includes Analog Devices AD9361 RF Agile Transceiver. The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

Source: © by Analog Devices, Inc. (ADI), May 2017. Reproduced with permission from ADI.

For more information, refer to the AD9361 site [2].

Analog Filters

Transmit Path

The transmitter section consists of two identical and independently controlled channels that provide all digital processing, mixed signal, and RF blocks necessary to implement a direct conversion system while sharing a common frequency synthesizer. The digital data received from the Baseband Processors (BBP) passes through a fully programmable 128-tap FIR filter with interpolation options. The FIR output is sent to a series of interpolation filters that provide additional filtering and data rate interpolation prior to reaching the DAC. Each 12-bit DAC has an adjustable sampling rate. Both the I and Q channels are fed to the RF block for upconversion.

The Raptor SDR includes two identical transmit ports. Each transmit port has 2 channels A and B .

Channel A contains a band pass filter with a frequency range of 2400 MHz to 2550 MHz and then it passes through an MGA-43228 power amplifier.MGA-43228 is a power amplifier for use in the (2.3-2.5)GHz band.
MGA-43228 Specifications :

• High gain: 38.5dB
• Low gain: 14.9dB
• High linearity performance: 29.2dBm at 5V supply (2.5% EVM, 64-QAM 3⁄4 FEC rate OFDMA, 10MHz bandwidth)

The power amplifier can operate in low gain or high gain mode and this setting is configurable through the AD9361 general purpose output 3 (GPO_3) pin. The power amplifier can be bypassed/enabled through GPO_2 pin.

Channel B is bypass channel.The figure below shows a simplified illustration of the transmit path and the ways it can be configured.

Receive Path

The receiver path contains two independently controlled channels that can receive signals from different sources, allowing the device to be used in multiple input, multiple output (MIMO) systems while sharing a common frequency synthesizer. Each channel has three inputs that can be multiplexed to the signal chain, making the AD9361 suitable for use in diversity systems with multiple antenna inputs. The receiver is a direct conversion system that contains a low noise amplifier (LNA), followed by matched in-phase (I) and quadrature (Q) amplifiers, mixers, and band shaping filters that down convert received signals to baseband for digitization. External LNAs can also be interfaced to the device, allowing designers the flexibility to customize the receiver front end for their specific application.

The Raptor SDR receive path contains four-band pre-selector per receiver channel that are run-time configurable by using the GPO_0 and GPO_1 bits. The Figure below shows a high level diagram of the receive path.

The following table explains the GPO configuration needed to select each filter.

Memory

DDR4

The Raptor board includes four Micron MT40A512M16HA-083E DDR4-2400 memory components, totaling 4GB of random access memory. The DDR4 memory is wired to the Zynq Ultrascale+ DDRC hard memory controller. DDR4 connections between Zynq Ultrascale+ DDRC hard memory controller and memory components are shown in the table below.

Notes:

1. U* - All memory components share the same connection.

On-chip Memory

The Xilinx Zynq UltraScale+ has 256 KB of on-chip memory (OCM) RAM. Accesses to the OCM must pass through the OCM protection unit, OCM_XMPU. The entire 256 KB of RAM is divided into 64 blocks (4 KB each) and assigned security attributes independently.

Quad SPI Flash

Raptor SDR includes dual Micron MT25QU512ABB8E12 serial NOR flash Quad-SPI memories that are capable of holding the boot image of the MPSoC system. To achieve higher performance two Quad-SPI devices are connected in parallel and provide an 8-bit data bus for booting and configuration.

The dual Quad-SPI flash memory located at U37/U39 provide 1 Gbit of non-volatile storage that can be used for booting, configuration and data storage. The connections between the flash memory and the XCZU9EG MPSoC are shown in the table below.

The table below shows the QSPI boot modes that the Raptor SDR support.

The configuration and Quad-SPI sections of the Zynq Ultrascale+ MPSoC Technical Reference Manual (UG1085) provide more details on using Quad-SPI. For more details about the Micron MT25QU512ABB8E12 see the datasheet at the Micron website.

EEPROM

The Raptor SDR includes a M24256-DFDW6 EEPROM. The M24256 is a 256-Kbit I2C compatible EEPROM organized as 32K x 8 bits and it operates with a supply voltage of 1.8 V. The connections between the flash memory and the XCZU9EG MPSoC are shown in the table below.

Micro SD

The Raptor board includes a secure digital input/output(SDIO) interface to provide access to general purpose non-volatile SDIO memory cards and peripherals.The Raptor SD card interface supports the SD1 configuration boot mode documented in the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085).

Interface

Installing and removing the microSD Card

The microSD card slides into a spring-loaded slot on the back of the Raptor board.

To install the card:

1. Power off the Raptor board.
2. Align the microSD card with the print facing up and the smallest edge toward the slot.
3. Use your fingertip to gently slide the card into the slot. When you feel some resistance, gently press the card a little farther until you hear a click, which indicates the spring-lock engaged.
4. Remove your finger from the card, which will spring out slightly to the fully inserted position. If the card springs out to the released position, press it in again until it remains in the fully inserted position.

To remove the card:

1. Power off the Raptor board.
2. Gently press the card into the slot with your fingertip until you hear a click, which indicates the spring-lock released.
3. From the released position, slide the card away from the board.

USB 2.0/3.0 Host Device

The Zynq® UltraScale+™ MPSoC USB 3.0 controller consists of two independent dual-role device (DRD) controllers. The Raptor SDR includes 2 USB ports that can be individually configured to work as host or device at any given time.

USB 2.0/3.0 Host Device Port 0

The table below shows the pin assignments for USB port 0.

USB 2.0/3.0 Host Device Port 1

The table below shows the pin assignments for USB port 1.

IO

User LEDs

The following tables summarize bank and signal assignments for the USER LEDs.

Expansion Header

The following tables summarize bank and signal assignments on the J14 connector.

Reset Sources

ZynqMP Power‐on Reset (PS_POR_B)

Depressing and then releasing pushbutton SW2 causes net PS_POR_B to strobe Low. This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal.

AD9361 Reset

The AD9361 has a single asynchronous reset pin (RESETB) that is connected directly to the ZynqMP SoC on Bank 66 – pin N11. Asserting this signal to logic low resets the device and triggers the automatic initialization calibrations. This signal is managed by the AD9361 device driver.

RF Interfaces and Timing Inputs

The Raptor SDR board has both GPS timing signal input connectors and RX/TX RF connectors. The GPS timing signal inputs are required for precision signal collection and data processing. The RF front end uses the GPS 10 MHz signal to derive the data collection clock and subsequently to drive all the processing logic in the FPGA. The 1 PPS signal is required for determining subsample timing precision. Refer to the table below for the electrical specification.

The RF RX inputs and TX outputs are all 50 Ohm impedance connections. The table below outlines the electrical specifications for these signals.

The Frequency Range column of the table below details the generic build options of the RF paths for the Raptor SDR. These frequency ranges are build time options and are made to order over the 70 MHz to 6 GHz range.

Expansion Board

1G Ethernet

The Raptor board uses TIDP83867IR Ethernet RGMII PHY at U13 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s.The PHY connection to a user-provided Ethernet cable is through a Bel Fuse 0826-1X1T-32-F RJ-45 connector (J4).

The Ethernet connections from XCZU9EG MPSOC to the TIDP83867IR PHY device at U13 are listed in the below table.

SFP+

The Raptor Expansion board contains a dual SFP+ interface to support data rates up to 10 Gbit/s.

The following tables list the connections between the connectors and the XCZU9EG MPSoC.

Firefly

The Samtec Firefly interface features 14 Gbit/s high speed data lanes. It has two transmit and two receive lanes.

The following table list the connections between the connectors and the XCZU9EG MPSoC.

Display Port

The Raptor board provides a VESA DisplayPort 1.2 source-only controller that supports up to two lanes of main link data at rates of 1.62 Gb/s, 2.70 Gb/s, or 5.40 Gb/s. The DisplayPort AUX channel is a half-duplex bidirectional data channel used for miscellaneous additional data beyond video and audio. In the Raptor board the AUX channel is connected to BANK 48.

The Raptor project is default to have the display port configure for a single lane. Lane 0 is shared with SATA through a switch. The selection can be configure by using the ps_dp_sel bit that is connected to the i2c (U19) expander.

M.2 SATA

The M.2 SATA SSD controller is connected to the FPGA on the following pins:

Multi-Interface Connector

The Multi-Interface connector provide 16 GPIO pins as well as a link for the XCZU9EG I2C, SPI and UART1. The figure below shows the PIN assignment for each of the interfaces.

I2C

The I2C bus allows for intra-board communication from the XCZU9EG MPSOC to the EEPROM, AD5593, and the Multi_Interface connector.

Base Board

Expansion Board

SPI

The SPI bus provides a communication link between the FPGA and the Multi-Interface Connector.

RS232

PS-side UART1 is available through J10 connector and through the expansion header. The connections from XCZU9EG UART1 to J10 and Expansion header are listed in the tables below.

AD5593

The AD5593R has eight I/Ox pins (I/O0 to I/O7) that can be independently configured as digital-to-analog converter (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. When an I/Ox pin is configured as an analog output, it is driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF. When an I/Ox pin is configured as an analog input, it is connected to a 12-bit ADC via an analog multiplexer. The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC has a total throughput rate of 400 kSPS. The I/Ox pins can also be configured as digital, general-purpose input or output (GPIO) pins. The state of the GPIO pins can be set or read back by accessing the GPIO write data register or the GPIO read configuration register, respectively, via an I2C write or read operation. The AD5593R have an integrated 2.5 V, 25 ppm/°C reference, which is turned off by default, and an integrated temperature indicator, which gives an indication of the die temperature. The temperature value is read back as part of an ADC read sequence.

The Raptor board brings the first four ports to the the multi-interface connector.

16x GPIO

The Multi-Interface Connector allows the user to pro grammatically set 16 GPIO pins that are directly connected to the FPGA. The interface is 3.3 V Bi-directional and 5 V toloerant.

IRIG-B

The IRIG-B connector allows the transferring of precise timinig information at a 100 Hz bit rate.